R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 906

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 23 Serial Protocol Interface (HSPI)
23.3.2
SPSR is a 32-bit readable/writable register. The status flag in SPSR can confirm whether the HSPI
correctly operates or not. If the ROIE bit in SPSCR is set to 1, an interrupt request is generated
due to the occurrence of the receive buffer overrun error or the warning of the receive buffer
overrun error. When the TFIE bit in SPSCR is set to 1, an interrupt request is generated by the
transmit complete status flag. If the appropriate enable bit in SPSCR is set to 1, an interrupt
request is generated due to the receive FIFO halfway, receive FIFO full, transmit FIFO empty, or
transmit FIFO halfway flag. If the RNIE bit in SPSCR is set to 1, an interrupt request is generated
when the receive FIFO is not empty.
Rev.1.00 Dec. 13, 2005 Page 854 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 11 
10
9
R/W:
R/W:
Bit:
Bit:
Status Register (SPSR)
Bit Name
TXFU
TXHA
31
15
—
—
—
—
R
R
30
14
—
—
—
—
R
R
Initial
Value
Undefined R
0
0
29
13
—
—
—
—
R
R
28
12
—
—
—
—
R
R
27
—
—
11
—
—
R
R/W
R
R
R
TXFU
26
10
—
—
R
R
0
Description
Reserved
These bits are always read as an undefined value. The
write value should always be 0.
Transmit FIFO Full Flag
This status flag is enabled only to operation in FIFO
mode. The flag is set to 1 when the transmit FIFO is full
of bytes for transmission and cannot accept any more.
It is cleared to 0 when data is transmitted from the
transmit FIFO.
Transmit FIFO Halfway Flag
This status flag is enabled only to operation in FIFO
mode. The flag is set to 1 when the transmit FIFO
reaches the halfway point, that is, it has 4 bytes of data
and 4 spaces for more data. It is cleared to 0 when
more data is written to the transmit FIFO. It remains set
to 1 until cleared to 0 even if the subsequent FIFO level
becomes under the halfway point (4 bytes).
If TXHA = 1 and THIE = 1 then the interrupt is
generated.
TXHA
25
—
—
R
R
9
0
TXEM
24
—
—
R
R
8
1
RXFU
23
—
—
R
R
7
0
RXHA
22
—
—
R
R
6
0
RXEM
21
—
—
R
R
5
1
RXOO
R/W
20
—
—
R
4
0
RXOW
R/W
19
—
—
R
3
0
RXFL
18
—
—
R
R
2
0
TXFN
17
—
—
R
R
1
0
TXFL
16
—
—
R
R
0
0