R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 511

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(4)
This status register is used to record status information for PCI bus related events. The definition
of each of the bits is given in the table below. A device may not need to implement all the bits,
depending on device functionality. For instance, since a device that acts as a target does not inform
a target abort, bit 11 does not need to be implemented. Reserved bits should be read-only and
return zero when the bits are read.
Reads from this register operates normally. Writes are slightly different in that bits can be cleared,
but not set. A one bit is cleared whenever the register is written to, and the write data in the
corresponding bit location is a 1. For instance, to clear bit 14 and not affect any other bits, write
the value of B'0100 0000 0000 0000 to the register.
Initial value:
Bit
15
14
PCI R/W:
SH R/W:
PCI Status Register (PCISTATUS)
Bit:
Bit Name
DPE
SSE
R/WC R/WC
R/WC R/WC
DPE
15
0
SSE
14
0
R/WC
R/WC
RMA
Initial
Value
0
0
13
0
R/WC
R/WC
RTA
12
0
R/W
SH: R/WC
PCI: R/WC
SH: R/WC
PCI: R/WC
R/WC
R/WC
STA
11
0
10
R
R
0
DEVSEL
Description
Parity Error Detect Status
Indicates that a parity error has been detected in read
data when the PCIC is a master or in write data when
the PCIC is a target.
This bit must be set by the device whenever it detects
a parity error, even if parity error handling is disabled.
0: Device is not detecting parity error.
1: Device is detecting parity error.
System Error Output Status
Indicates that the PCIC has asserted the SERR
signal.
0: SERR has not been asserted
1: SERR has been asserted (the value retained until
R
R
9
1
cleared)
R/WC
R/WC
MDPE
8
0
FBBC
R
R
7
1
Rev.1.00 Dec. 13, 2005 Page 459 of 1286
R/W

R
6
0
R/W
66C
R
5
0
Section 13 PCI Controller (PCIC)
CL
R
R
4
1

R
R
3
0
REJ09B0158-0100

R
R
2
0

R
R
1
0

R
R
0
0