R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 25

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

25.4 AC 97 Frame Slot Structure............................................................................................... 973
25.5 Operation ........................................................................................................................... 974
Section 26 Serial Sound Interface (SSI) Module...............................................983
26.1 Features.............................................................................................................................. 983
26.2 Input/Output Pins ............................................................................................................... 984
26.3 Register Descriptions ......................................................................................................... 985
26.4 Operation ........................................................................................................................... 998
26.5 Usage Note....................................................................................................................... 1019
Section 27 NAND Flash Memory Controller (FLCTL) ..................................1021
27.1 Features............................................................................................................................ 1021
27.2 Input/Output Pins ............................................................................................................. 1024
27.3 Register Descriptions ....................................................................................................... 1025
25.3.7 TX Status Register (HACTSR)............................................................................. 967
25.3.8 RX Interrupt Enable Register (HACRIER)........................................................... 969
25.3.9 RX Status Register (HACRSR) ............................................................................ 970
25.3.10 HAC Control Register (HACACR) ...................................................................... 971
25.5.1 Receiver ................................................................................................................ 974
25.5.2 Transmitter............................................................................................................ 975
25.5.3 DMA ..................................................................................................................... 975
25.5.4 Interrupts............................................................................................................... 975
25.5.5 Initialization Sequence.......................................................................................... 976
25.5.6 Notes ..................................................................................................................... 981
25.5.7 Reference .............................................................................................................. 981
26.3.1 Control Register (SSICR) ..................................................................................... 986
26.3.2 Status Register (SSISR) ........................................................................................ 992
26.3.3 Transmit Data Register (SSITDR)........................................................................ 997
26.3.4 Receive Data Register (SSIRDR) ......................................................................... 997
26.4.1 Bus Format............................................................................................................ 998
26.4.2 Non-Compressed Modes....................................................................................... 999
26.4.3 Compressed Modes............................................................................................. 1008
26.4.4 Operation Modes................................................................................................. 1011
26.4.5 Transmit Operation ............................................................................................. 1012
26.4.6 Receive Operation............................................................................................... 1015
26.4.7 Serial Clock Control ........................................................................................... 1018
26.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation .......... 1019
27.3.1 Common Control Register (FLCMNCR)............................................................ 1026
27.3.2 Command Control Register (FLCMDCR).......................................................... 1028
27.3.3 Command Code Register (FLCMCDR) ............................................................. 1030
Rev.1.00 Dec. 13, 2005 Page xxiii of l