R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 899
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 899 of 1342
- Download datasheet (7Mb)
16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left-channel
transmit data, slot No.1 used for left-channel receive data, slot No.2 used for right-channel
transmit data, slot No.3 used for right-channel receive data, and frame length = 64 bits
16-bit Stereo Data (3): Synchronous pulse method, falling edge sampling, slot No.0 used for left-
channel data, slot No.1 used for right-channel data, slot No.2 used for control data for channel 0,
slot No.3 used for control data for channel 1, and frame length = 128 bits
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
Specifications:
Figure 22.17 Transmit and Receive Timing (16-Bit Stereo Data (2))
Figure 22.18 Transmit and Receive Timing (16-Bit Stereo Data (3))
Specifications:
Slot No.0
L-channel data
L-channel
No bit delay
Slot No.0
data
1 bit delay
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
TRMD[1:0] = 11,
TDLE = 1,
RDLE = 1,
CD0E = 0,
Slot No.1
R-channel
data
L-channel data
channel 0
Slot No.2
Control
Slot No.1
REDG = 1,
TDLA[3:0] = 0000,
RDLA[3:0] = 0001,
CD0A[3:0] = 0000,
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] =0010,
1 frame
Slot No.3
channel 1
Control
1 frame
R-channel data
FL[3:0] = 1101 (frame length: 64 bits),
TDRE = 1,
RDRE = 1,
CD1E = 0,
Slot No.4
Slot No.2
FL[3:0] = 1110 (frame length: 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
Rev.1.00 Dec. 13, 2005 Page 847 of 1286
Section 22 Serial I/O with FIFO (SIOF)
Slot No.5
TDRA[3:0] = 0010,
RDRA[3:0] = 0011,
CD1A[3:0] = 0000
R-channel data
TDRA[3:0] = 0001,
RDRA[3:0] = 0001,
CD1A[3:0] = 0011
Slot No.3
Slot No.6
REJ09B0158-0100
Slot No.7
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