R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 458

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 DDR-SDRAM Interface (DDRIF)
12.3.3
The DDRIF supports both big endian mode, where the address of the highest order byte is 0, and
little endian mode, where the address of the lowest order byte is 0. These modes can be switched
by changing the level on an external pin (MODE5) and then generating a power-on reset. Note
that wraparound in memory data access is on 32-byte boundaries.
Table 12.2 Access and Data Alignment in Little Endian Mode
Rev.1.00 Dec. 13, 2005 Page 406 of 1286
REJ09B0158-0100
Byte access at address 0
Byte access at address 1
Byte access at address 2
Byte access at address 3
Byte access at address 4
Byte access at address 5
Byte access at address 6
Byte access at address 7
Word access at address 0
Word access at address 2
Word access at address 4
Word access at address 6
Longword access at address 0
Longword access at address 4
Quadword access at address 0
(first round: from address 0)
Quadword access at address 0
(second round: from address 4)
16-byte access at address 0
(first round: from address 4)
16-byte access at address 0
(second round: from address 0)
16-byte access at address 0
(third round: from address 12 (H'C))
16-byte access at address 0
(fourth round: from address 8)
Data Alignment
MD31 to MD24 MD23 to MD16 MD15 to MD8
Bit 7 to 0
Bit 7 to 0
Bit 15 to 8
Bit 15 to 8
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 63 to 56
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 55 to 48
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 7 to 0
Bit 7 to 0
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 47 to 40
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
MD7 to MD0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 39 to 32
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0

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