R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 833
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 833 of 1342
- Download datasheet (7Mb)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
Figure 21.13 shows an example of the operation for reception in asynchronous mode.
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
(a) Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
(b) The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.*
(c) Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun
(d) Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Note: * Reception continues even when a parity error or framing error occurs.
the first is checked.
error has occurred.*
set.*
If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR.
Section 21 Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Dec. 13, 2005 Page 781 of 1286
REJ09B0158-0100
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