R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 926

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 24 Multimedia Card Interface (MMCIF)
In write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, the data transmission should be
temporarily halted by FIFO full/empty, and it should be resumed when the preparation has been
completed.
In multiple block transfer, the transfer should be temporarily halted at every block break to select
either to continue to the next block or to abort the multiple block transfer command by issuing the
CMD12 command. To continue to the next block, the RD_CONTI and DATAEN bits should be
set to 1. To issue the CMD12 command, the CMDOFF bit should be set to 1 to abort the command
sequence on the MMCIF side. When using the auto-mode for a pre-defined multiple block
transfer, the setting of the RD_CONTI bit or the DATAEN bit between blocks can be omitted.
Rev.1.00 Dec. 13, 2005 Page 874 of 1286
REJ09B0158-0100
Bit
4
3 to 0
Bit Name
DATAEN
—
Initial
Value
0
All 0
R/W
R/W
R
Description
Data Enable
Starts a write data transmission by a command with
write data. This bit is cleared automatically when 1 is
written and the MMCIF received the DATAEN
command. Resumes write data transmission while the
sequence has been halted by FIFO empty or
termination of block writing in multiple block write.
Write enabled period: (1) after receiving a response to a
command with write data, (2) while sequence is halted
by FIFO empty, (3) when one block writing in multiple
block write is terminated.
Write of 0: Operation is not affected.
Write of 1: Starts or resumes write data transmission.
Note: Do not write to this bit out of the write enable
Reserved
These bits are always read as 0. The write value should
always be 0.
period.