R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 422

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Local Bus State Controller (LBSC)
11.5.4
Burst ROM (Clock Asynchronous) Interface
Setting the TYPE bit in CSnBCR (n = 0 to 2 and 4 to 6) to 010 allows a burst ROM (clock
asynchronous memory) to be connected to areas 0 to 2 and 4 to 6. The burst ROM interface
provides high-speed access to ROM that has a burst access function. The burst access timing of
burst ROM is shown in figure 11.11. The wait cycle is set to 0 cycle. Although the access is
similar to that of the SRAM interface, only the address is changed when the first cycle ends and
then the next access is started. When 8-bit ROM is used, the number of consecutive accesses can
be set as 4, 8, 16, or 32 through bits BST2 to BST0 in CSnBCR (n = 0 to 2 and 4 to 6). Similarly,
when 16-bit ROM is used, 4, 8 or 16 accesses can be set; when 32-bit ROM is used, 4 or 8
accesses can be set.
The RDY signal is always sampled when one or more wait cycles are set.
Even when no wait is specified in the burst ROM settings, two access cycles are inserted in the
second and subsequent accesses as shown in figure 11.12.
A writing operation for this interface is performed in the same way as for the SRAM interface.
In a 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus
width. The first access is performed on the data for which there was an access request, and the
remaining accesses are performed in wraparound method according to the set bus width. The burst
access is stopped once (negate the RD) at the address boundary which is a bus width
(CSnBCR.SZ) x burst length (CSnBCR.BST) address and then the access is resumed by the
settings of CSnWCR. The bus is not released during this transfer.
Figure 11.13 shows the timing chart when the burst ROM is used and setup/hold is specified by
CSnWCR.
Rev.1.00 Dec. 13, 2005 Page 370 of 1286
REJ09B0158-0100