R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 690

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Watchdog Timer and Reset
PRESET input during Sleep Mode
It is necessary to ensure the PLL oscillation time when power-on reset generates by the PRESET
pin low revel input during sleep mode.
16.5.2
The transition time from the watchdog timer overflowed to the power-on reset state (watchdog
timer reset setup time) is 1 clock cycle of the XTAL clock and thereafter equal to or more than 5
clock cycles of the peripheral clock (Pck).
The power-on reset time (watchdog timer reset holding time) by the watchdog timer overflowed is
3774 clock cycles of the XTAL clock and thereafter equal to or more than 45 clock cycles of the
peripheral clock (Pck).
The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is
asynchronous with both the XTAL clock and the CLKOUT pin output clock because the STATUS
[1:0] pins output timing is synchronous with the peripheral clock (Pck).
Rev.1.00 Dec. 13, 2005 Page 638 of 1286
REJ09B0158-0100
Power-On Reset by Watchdog Timer Overflow
XTAL
(oscillator)
CLKOUT
output
PRESET
input
STATUS[1:0]
output
Figure 16.5 STATUS Output by Reset input during Sleep Mode
HL (sleep)
PLL synchronization
settling time
HH (reset)
Reset holding
time
LL (normal)