R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 634

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Rev.1.00 Dec. 13, 2005 Page 582 of 1286
REJ09B0158-0100
Bit
9, 8
7 to 3
2
Bit Name
PR[1:0]
—
AE
Initial
Value
00
0
All 0
R/W
R/W
R
R/(W)* Address Error Flag
Descriptions
Priority Mode 1, 0
Select the priority level between channels when there
are transfer requests for multiple channels
simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 (DMAOR0)
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5 (DMAOR0)
10: Setting prohibited
11: Round-robin mode
When round-robin mode is specified, do not mix the
cycle steal mode and the burst mode in channels 0 to 5
or 6 to 11 respectively.
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates that an address error occurred during DMA
transfer.
This bit is set under following conditions:
•
•
•
If this bit is set, the corresponding channels (channels 0
to 5 or 6 to 11) DMA transfer are all disabled even if the
DE bit in each CHCR and the DME bit in corresponding
DMAOR are set to 1.
0: No DMAC address error
[Clearing condition]
Writing AE = 0 after AE = 1 read
1: DMAC address error occurs
The value set in SAR or DAR does not match to the
transfer size boundary.
The transfer source or transfer destination is invalid
space.
The transfer source or transfer destination is in
module stop mode
CH6 > CH7 > CH8 > CH9 > CH10 > CH11
(DMAOR1)
CH6 > CH8 > CH9 > CH7 > CH10 > CH11
(DMAOR1)