R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 837

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Set RTRG1-0 and TTRG1-0 bits
in SCSCR (leaving TE, RE, TIE,
in SCFCR, and clear TFCL and
Set TE and RE bits in SCSCR
Set external pins to be used
and RIE bits cleared to 0)
Set CKE1 and CKE0 bits
(SCIF_SCK, SCIF_TXD,
Set TFCL and RFCL bits
and ER flags in SCFSR,
Set data transfer format
After reading BRK, DR,
in SCFCR to 1 to clear
1-bit interval elapsed?
to 1, and set TIE, RIE,
write 0 to clear them
Clear TE and RE bits
Set value in SCBRR
Start of initialization
End of initialization
the FIFO buffer
and SCIF_RXD)
RFCL bits to 0
in SCSCR to 0
and REIE bits
Figure 21.16 Sample SCIF Initialization Flowchart
in SCSMR
Yes
Wait
No
[1]
[2]
[3]
[4]
[5]
[6]
Section 21 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
[6]
Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
Set the CKE1 and CKE0 bits.
Set the data transfer format in
SCSMR.
Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used. Wait at least one
bit interval after this write before
moving to the next step.
Set the external pins to be used.
Set SCIF_RXD input for reception and
SCIF_TXD output for transmission.
The input/output of the SCIF_SCK pin
must match the setting of the CKE1
and CKE0 bits.
Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the SCIF_TXD,
SCIF_RXD, and SCIF_SCK pins to
be used. When transmitting, the
SCIF_TXD pin will go to the mark
state. When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCIF_SCK pin
at this point.
Rev.1.00 Dec. 13, 2005 Page 785 of 1286
REJ09B0158-0100