R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 816

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
21.3.12 Serial Port Register n (SCSPTR)
SCSPTR is a 16-bit readable/writable register that controls input/output and data for the port pins
multiplexed with the serial communication interface (SCIF) pins at all times. Input data can be
read from the SCIF_RXD pin, output data written to the SCIF_TXD pin, and breaks in serial
transmission/reception controlled, by means of bits 1 and 0.
All SCSPTR bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset;
the value of bits 6, 4, 2, and 0 is undefined. SCSPTR is not initialized in the module standby state.
Note that when reading data via a serial port pin in the SCIF, the peripheral clock value from 2
cycles before is read.
Rev.1.00 Dec. 13, 2005 Page 764 of 1286
REJ09B0158-0100
Initial value:
Bit
15 to 8
7
Note: * Reserved bit in channel 1.
R/W:
Bit:
Bit Name
—
RTSIO*
15

R
0
14

R
0
13

R
0
Initial
Value
All 0
0
12

R
0
11

R
0
R/W
R
R/W
10

R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Serial Port SCIF0_RTS Port Input/Output
Specifies the serial port SCIF0_RTS pin input/output
condition. When actually setting the SCIF0_RTS pin as
a port output pin to output the value set by the RTSDT
bit, the MCE bit in SCFCR should be cleared to 0.
0: RTSDT bit value is not output to SCIF0_RTS pin
1: RTSDT bit value is output to SCIF0_RTS pin

R
0
9

R
8
0
R/W
RTS
IO
7
0
*
R/W
RTS
DT

6
*
R/W
CTS
IO
5
0
*
R/W
CTS
DT

4
*
R/W
SCK
IO
3
0
R/W
SCK
DT

2
SPB2
R/W
IO
1
0
SPB2
R/W
DT

0