R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 904

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 23 Serial Protocol Interface (HSPI)
23.3.1
SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and
specifies the clock polarity and frequency.
Rev.1.00 Dec. 13, 2005 Page 852 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 8
7
6
R/W:
R/W:
Bit:
Bit:
Control Register (SPCR)
Bit Name

FBS
CLKP
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
29
13
—
—
Initial
Value
All 0
0
0
R
R
0
0
28
12
—
—
R
R
0
0
27
—
11
—
R
R
0
0
R/W
R
R/W
R/W
26
10
—
—
R
R
0
0
Description
Reserved
Although the initial value is 0, these bits will be read as
an undefined value. The write value should always be 0.
First Bit Start
Controls the timing relationship between each bit of
transferred data and the serial bit clock.
0: The first bit transmitted from the HSPI module is set
1: The first bit transmitted from the HSPI module is set
Serial Clock Polarity
0: HSPI_CLK signal is not inverted and so is low when
1: HSPI_CLK signal is inverted and so is high when
up such that it can be sampled by the receiving
device on the first edge of HSPI_CLK after the
HSPI_CS pin goes low. Similarly the first received bit
is sampled on the first edge of HSPI_CLK after the
HSPI_CS pin goes low.
up such that it can be sampled by the receiving
device on the second edge of HSPI_CLK after the
HSPI_CS pin goes low. Similarly the first received bit
is sampled on the second edge of HSPI_CLK after
the HSPI_CS pin goes low.
inactive.
inactive.
25
—
—
R
R
0
9
0
24
—
—
R
R
0
8
0
FBS
R/W
23
—
R
0
7
0
CLKP
R/W
22
—
R
0
6
0
IDIV
R/W
21
—
R
0
5
0
CLKC4
R/W
20
—
R
0
4
0
CLKC3
R/W
19
—
R
0
3
0
CLKC2
R/W
18
—
R
0
2
0
CLKC1
R/W
17
—
R
0
1
0
CLKC0
R/W
16
—
R
0
0
0