R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 834

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
5. When modem control is enabled, the SCIF0_RTS signal is output when SCFRDR is empty.
Figure 21.14 shows an example of the operation when modem control is used.
Rev.1.00 Dec. 13, 2005 Page 782 of 1286
REJ09B0158-0100
When SCIF0_RTS is 0, reception is possible. When SCIF0_RTS is 1, this indicates that
SCFRDR contains bytes of data equal to or more than the SCIF0_RTS output active trigger
number. The SCIF0_RTS output active trigger value is specified by bits 10 to 8 in the FIFO
control register (SCFCR). For details, see section 21.3.9, FIFO Control Register n (SCFCR). In
addition, SCIF0_RTS is also 1 when the RE bit in SCSCR is cleared to 0.
RDF
FER
SCIF_RXD
SCIF0_RTS
Serial data
Figure 21.14 Sample Operation Using Modem Control (SCIF0_RTS)
Serial
data
1
Start
bit
0
Start
bit
0
(Example with 8-Bit Data, Parity, One Stop Bit)
D0
Figure 21.13 Sample SCIF Receive Operation
D0
D1 D2
One frame
D1
Data
(Only in Channel 0)
D7 0/1 1
D7
RXI interrupt
request
Parity
bit
Parity
bit
0/1
Stop
bit
Stop
bit
1
Start
bit
0
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
D0
D1
Start
bit
Data
0
D7
Parity
bit
0/1
Stop
bit
ERI interrupt request
generated by receive
error
0
Detect flaming
error
0/1