R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 653

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 14.10 DMA Transfer Matrix in Peripheral module Request Mode
[Legend]
Yes:
No:
Note:
Bus Mode and Channel Priority: When the priority is set in fixed mode (CH0 > CH1) and
channel 1 is transferring in burst mode, if there is a transfer request to channel 0 with a higher
priority, the transfer of channel 0 will begin immediately.
At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue after
the channel 0 transfer has completely finished.
When channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of
one transfer unit and the channel 1 transfer is continuously performed without releasing the bus
mastership. The bus mastership will then switch between the two in the order channel 0, channel
1, channel 0, and channel 1.
This example is shown in figure 14.9. When multiple channels are operating in burst modes, the
channel with the highest priority is executed first.
When DMA transfer is executed in the multiple channels, the bus mastership will not be given to
the bus master until all competing burst transfers are complete.
Transfer Source
LBSC space
DDRIF space
PCIC space
Peripheral module*
L RAM, SuperHyway RAM No
Transfer is available.
Transfer is not available.
*
When the transfer source or the destination is an peripheral module, the transfer size
should be the same value of its register access size.
The transfer source or the transfer destination should be a register of request source in
peripheral module request mode. This transfer is available only cycle steal mode, and
when the transfer request source is an peripheral module, the transfer is available in
channel 0 to 5.
LBSC space DDRIF space PCIC space
No
No
No
Yes
No
No
No
Yes
No
Section 14 Direct Memory Access Controller (DMAC)
Transfer Destination
No
No
No
Yes
No
Rev.1.00 Dec. 13, 2005 Page 601 of 1286
Peripheral
module*
Yes
Yes
Yes
Yes
Yes
REJ09B0158-0100
L RAM,
SuperHyway
RAM
No
No
No
Yes
No