R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 341
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 341 of 1342
- Download datasheet (7Mb)
INT2B3: Indicates detailed interrupt sources for the DMAC.
Note: The DMA transfer end or half-end interrupt means the transfer has finished or half finished
Module
DMAC
with the condition of specified to the corresponding TCR.
Bit
31 to 14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
DMAE1
DMAE0
DMINT11
DMINT10
DMINT9
DMINT8
DMINT7
DMINT6
DMINT5
DMINT4
DMINT3
DMINT2
DMINT1
DMINT0
Detailed Source
(Reserved)
These bits are always read
as 0. Writing to these bits is
invalid.
DMA channels 6 to 11
address error interrupt
DMA channels 0 to 5
address error interrupt
Channel 11 DMA transfer
end or half-end interrupt
Channel 10 DMA transfer
end or half-end interrupt
Channel 9 DMA transfer
end or half-end interrupt
Channel 8 DMA transfer
end or half-end interrupt
Channel 7 DMA transfer
end or half-end interrupt
Channel 6 DMA transfer
end or half-end interrupt
Channel 5 DMA transfer
end or half-end interrupt
Channel 4 DMA transfer
end or half-end interrupt
Channel 3 DMA transfer
end or half-end interrupt
Channel 2 DMA transfer
end or half-end interrupt
Channel 1 DMA transfer
end or half-end interrupt
Channel 0 DMA transfer
end or half-end interrupt
Rev.1.00 Dec. 13, 2005 Page 289 of 1286
Section 10 Interrupt Controller (INTC)
Description
Indicates DMAC interrupt
sources. This register indicates
DMAC interrupt sources even if
a mask setting for DMAC
interrupts has been made in the
interrupt mask register.
REJ09B0158-0100
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