R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 473

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12.4.4
Initial value:
Initial value:
Initial value:
Initial value:
Bit
1
0
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
SDRAM Row Attribute Register (SDR)
Bit Name
SRCD
SRP
63
47
31
15




R
R
R
R
0
0
0
0
62
46
30
14




R
R
R
R
0
0
0
0
61
45
29
13




R
R
R
R
0
0
0
0
Initial
Value
0
0
60
44
28
12




R
R
R
R
0
0
0
0
R/W
R/W
R/W
R/W
59
43
27
11



R
R
R
0
0
0
0
R/W
58
42
26
10



R
R
R
0
0
0
0
SPLIT
Description
Numbers of Cycles between RAS and CAS Commands
Specifies the number of cycles from an RAS (ACT)
command to a subsequent CAS (READ/READA,
WRITE/WRITEA) command (the corresponding time is
tRCD).
0: 3 cycles
1: 4 cycles
Number of Cycles between PRE and ACT Commands
Specifies the number of cycles from a PRE command
to a subsequent ACT command (the corresponding
time is tRP).
0: 3 cycles
1: 4 cycles
R/W
57

41

25

R
R
R
0
0
0
9
0
R/W
56

40

24

R
R
R
0
0
0
8
1
55
39
23




R
R
R
R
0
0
0
7
0
Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 421 of 1286
54
38
22




R
R
R
R
0
0
0
6
0
53
37
21




R
R
R
R
0
0
0
5
0
52
36
20




R
R
R
R
0
0
0
4
0
51
35
19




R
R
R
R
0
0
0
3
0
REJ09B0158-0100
50
34
18




R
R
R
R
0
0
0
2
0
49

33

17


R
R
R
R
0
0
0
1
0
47

32

16


R
R
R
R
0
0
0
0
0