R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 630

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Rev.1.00 Dec. 13, 2005 Page 578 of 1286
REJ09B0158-0100
Bit
11 to 8
7
6
5
4, 3
Bit Name
RS[3:0]
DL
DS
TB
TS[1:0]
Initial
Value
0000
0
0
0
00
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
Resource Select 3 to 0
Specify which transfer requests will be sent to the
DMAC. The changing of transfer request source should
be done in the state that the DMA enable bit (DE) is
cleared to 0.
0000: External request, dual address mode
0100: Auto request
1000: Selected by DMA extended resource selector (for
Other than above: Setting prohibited
Note: External request specification is valid only in
DREQ Level and DREQ Edge Select
Specify the detecting method of the DREQ pin input
and the detecting level.
These bits are valid only in CHCR0 to CHCR3.
In channels 0 to 3, also, if the transfer request source is
specified as a peripheral module or if an auto-request is
specified, these bits are invalid.
00: DREQ detected in low level (DREQ)
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
Select the cycle steal mode when the peripheral module
requests.
DMA Transfer Size Specify
See the description of TS2 (bit 20).
peripheral modules)
CHCR0 to CHCR3. None of the external request
can be selected in CHCR4 to CHCR11. DMA
extended resource selector is valid only in
CHCR0 to CHCR5).