R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 347

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 10.10 shows the correspondence between the interrupt input pins and bits in INT2GPIC.
Table 10.10 Correspondence between Interrupt Input Pins and Bits in INT2GPIC
Bit
31 to
26
25
24
23 to
20
19
18
17
16
15 to
11
10
9
8
7 to
3
2
1
0
Initial
Value R/W Name
All 0
0
0
All 0
0
0
0
0
All 0
0
0
0
All 0
0
0
0
R/W (Reserved)
R/W PORTE6E
R/W PORTK5E
R/W (Reserved)
R/W PORTK4E
R/W PORTJ0E
R/W PORTH1E
R/W PORTH0E
R/W (Reserved)
R/W PORTE5E
R/W PORTE4E
R/W PORTE3E
R/W (Reserved)
R/W PORTE2E
R/W PORTE1E
R/W PORTE0E
Function
These bits are always read
as 0. The write value should
always be 0.
Enables interrupt request
from pin 6 of port E.
Enables interrupt request
from pin 5 of port K.
These bits are always read
as 0. The write value should
always be 0.
Enables interrupt request
from pin 4 of port K.
Enables interrupt request
from pin 0 of port J.
Enables interrupt request
from pin 1 of port H.
Enables interrupt request
from pin 0 of port H.
(Initial value: all 0)
Enables interrupt request
from pin 5 of port E.
Enables interrupt request
from pin 4 of port E.
Enables interrupt request
from pin 3 of port E.
These bits are always read
as 0. The write value should
always be 0.
Enables interrupt request
from pin 2 of port E.
Enables interrupt request
from pin 1 of port E.
Enables interrupt request
from pin 0 of port E.
Rev.1.00 Dec. 13, 2005 Page 295 of 1286
Section 10 Interrupt Controller (INTC)
Description
Enables a GPIO interrupt
request for each pin.
0: Disables the corresponding
1: Enables the corresponding
interrupt request
interrupt request
REJ09B0158-0100