R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 824
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 824 of 1342
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Section 21 Serial Communication Interface with FIFO (SCIF)
21.4.2
In asynchronous mode, a character that consists of data with a start bit indicating the start of
communication and a stop bit indicating the end of communication is transmitted or received. In
this mode, serial communication is performed with synchronization achieved character by
character.
Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and receiver have a 64-stage FIFO buffer structure, so that
data can be read or written during transmission or reception, enabling continuous data
transmission and reception.
Figure 21.7 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCIF monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One character in serial communication consists of a start bit (low level), followed by
transmit/receive data (LSB-first; from the lowest bit), a parity bit (high or low level), and finally
stop bits (high level).
In reception in asynchronous mode, the SCIF synchronizes with the fall of the start bit. Receive
data can be latched at the middle of each bit because the SCIF samples data at the eighth clock
which has a frequency of 16 times the bit rate.
Rev.1.00 Dec. 13, 2005 Page 772 of 1286
REJ09B0158-0100
Serial
data
Operation in Asynchronous Mode
1
1 bit
Start
Figure 21.7 Data Format in Asynchronous Communication
bit
0
(Example with 8-Bit Data, Parity, and Two Stop Bits)
LSB
D0
D1
One unit of transfer data (character or frame)
D2
Transmit/receive data
D3
7 or 8 bits
D4
D5
D6
MSB
D7
1 bit or
none
Parity
0/1
bit
Stop bit
1
1 or 2 bits
1
(mark state)
Idle state
1
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