R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 530
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 13 PCI Controller (PCIC)
(26) PCI Power Management Control/Status Register (PCIPMCSR)
This 16-bit register is used to manage the PCI function's power management status as well as to
enable/monitor PMEs. For details, refer to “PCI Bus Power Management Interface Specification
Revision 1.1 Chapter 3 PCI Power Management Interface”.
Rev.1.00 Dec. 13, 2005 Page 478 of 1286
REJ09B0158-0100
Initial value:
Bit
15
14, 13
12 to 9
8
7 to 2
1, 0
PCI R/W:
SH R/W:
Bit:
Bit Name
PMES
DSC
DSL
PMEEN
PS
PMES
15
R
R
0
14
R
R
0
DSC
Initial
Value
0
00
0000
0
All 0
00
13
R
R
0
12
R
R
0
R/W
SH: R
PCI: R
SH: R
PCI: R
SH: R
PCI: R
SH: R
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R/W
11
R
R
0
DSL
10
R
R
0
Description
PME Status
Indicates the state of the PME signal.
(Not supported)
Note: This LSI dose not have the PME pin.
Data Scale
Specify the scaling of data field. (Not supported)
Data Select
Specify the data output in the data filed.
PME Enable
Controls the PME output. (Not supported)
Note: This LSI dose not have the PME pin.
Reserved
These bits are always read as 0. The write value
should always be 0.
Power State
Specifies the power state.
If software attempts to write an unsupported, optional
state to these bits, the write operation must complete
normally on the bus; however, the data is discarded
and no state change occurs.
00: D0 state
01: D1 state
10: D2 state
11: D3 hot state (power-down mode)
R
R
9
0
PME
EN
R
R
8
0
R
R
7
0
R
R
6
0
R
R
5
0
R
R
4
0
R
R
3
0
R
R
2
0
R/W
R
1
0
PS
R/W
R
0
0
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