R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 739

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note:
Bit
9, 8
7, 6
5
4
3
2
1
0
*
Bit Name
CC0
—
SI1
SI0
OP3
OP2
OP1
OP0
The source clock is the peripheral clock (Pck). The clock which divided from the source
clock is the timer/counter resolution of the channel.
Initial
Value
All 0
All 0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Free-Running Timer Clock Control
This clock is used for the 32-bit free-running timer (FRT)
and also for the 16-bit timer/counter in channel 0.*
00: Clock for FRT and timer 0 is 1/32 of peripheral clock
01: Clock for FRT and timer 0 is 1/128 of peripheral
10: Clock for FRT and timer 0 is 1/512 of peripheral
11: Clock for FRT and timer 0 is 1/1024 of peripheral
The clock which divided from the peripheral clock (Pck)
Reserved
These bits are always read as 0. The write value should
always be 0.
Channel 1 to 0 Stop Ignore
For the channel n, these bits determine whether in
output compare mode with 32-bit free-running timer
mode, the output remains active for half the maximum
time or until the stop value is reached.
0: Output remains active until the channel n stop time
1: Output remains active for half the total time of the FRT
n = 0, 1
Channel 3 to 0 Operation
For the channel n, if in timer mode, these bits determine
whether the timer is used in output compare or input
capture mode.
Set 1 to the corresponding bit when using channel 2 or 3
as the timer.
0: Input capture mode (can be set in channel 0, 1)
1: Output compare mode
When a channel is in output compare mode, the
corresponding IEEn bits has to be set to 0.
n = 3 to 0
is the timer/counter resolution.
value is reached
(Pck)
clock (Pck)
clock (Pck)
clock (Pck)
Rev.1.00 Dec. 13, 2005 Page 687 of 1286
Section 19 Compare Match Timer (CMT)
REJ09B0158-0100