R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 371

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Notes: 1. These pins are multiplexed with the GPIO pins.
Pin Name
IOIS16*
BREQ*
BACK
CE2A*
CE2B*
MODE3*
MODE4*
MODE5*
DACK0*
DACK1*
DACK2*
DACK3*
4
4
3
2. This pin is multiplexed with the TMU/RTC and GPIO pin.
3. This pin is multiplexed with the GPIO pin.
4. When bits TYPE2 to TYPE0 in the CS5 bus control register (CS5BCR) are set to b'100,
5. This pin is multiplexed with the INTC and FLCTL pin.
6. This pin is multiplexed with the SCIF, MMCIF and GPIO pin.
7. This pin is multiplexed with the MODE control and GPIO pin.
8. This pin is multiplexed with the MRESETOUT, H-UDI, and GPIO pin.
9. This pin is multiplexed with the INTC, H-UDI and GPIO pin.
10. Can be selectable the polarity (initial state is low active). For details, see section 14,
11. Can be selectable the polarity and detection edge (initial state is low active). For details,
,
2
7, 10
7, 10
8, 10
9, 10
5
5
6
,
CE2A act as PCMCIA output pin, and bits TYPE2 to TYPE0 in the CS6 bus control
register (CS6BCR) are set to B'100, CE2B act as PCMCIA output pin.
Direct Memory Access Controller (DMAC).
see section 14, Direct Memory Access Controller (DMAC).
Function
16-Bit I/O
Bus Release
Request
Bus Request
Acknowledge
PCMCIA Card
Select
Area 0 Bus
Width
Endian
Switchover
DMA channel 0
transfer end
notification
DMA channel 1
transfer end
notification
DMA channel 2
transfer end
notification
DMA channel 3
transfer end
notification
Input
I/O
Input
Output
Output
Input
Input
Output
Output
Output
Output
16-bit I/O signal when setting PCMCIA interface.
Bus release acknowledge signal
Description
Valid only in little endian mode
Bus release request signal
When setting PCMCIA, CE2A and CE2B
Signal setting area 0 bus width and MPX
interface at power-on reset
Endian setting at a power-on reset
Strobe output from channel 0 to external device
which has output DREQ0*
transfer request
Strobe output from channel 1 to external device
which has output DREQ1*
transfer request
Strobe output from channel 2 to external device
which has output DREQ2*
transfer request
Strobe output from channel 3 to external device
which has output DREQ3*
transfer request
Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 319 of 1286
11
11
11
11
, regarding DMA
, regarding DMA
, regarding DMA
, regarding DMA
REJ09B0158-0100