R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 364

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
10.7
10.7.1
When an IRQ level-sense interrupt request or IRL level-encoded interrupt request (IRQ/IRL level
interrupt request) is generated and the holding function is in use, the interrupt request must be
cleared in the interrupt handling routine after it has been accepted. Figure 10.5 shows an example
of an interrupt-handling routine to clear interrupt request holding in the detection circuit.
To cancel an interrupt request after its acceptance by the CPU, the external device that generated
the request must be notified of its acceptance. The method of notification might take the form of
using the GPIO to output the acceptance level or interrupt pin information, or writing to a special
address in the local bus space. It is necessary to consecutively execute writing to and reading from
the GPIO register or the special location in the local bus space.
After clearing an interrupt request that is held in the detection circuit, ensure that the time required
for the CPU to detect the interrupt has elapsed. To ensure this time, consecutively execute writing
to INTMSK0/1 and INTMSKCLR0/1 and reading of INTMSK0/1.
Rev.1.00 Dec. 13, 2005 Page 312 of 1286
REJ09B0158-0100
Usage Notes
To Clear Interrupt Request When Holding Function Selected
request holding in the detection circuit
external device interrupt requests and
using the GPIO output or writing to an
the IRQ/IRL level interrupt request by
Instruct the external device to cancel
and clear the IRQ interrupt source
level-encoded interrupt (IRQ/IRL
Allow time for the cancellation of
Clear the IRQ/IRL level interrupt
Figure 10.5 Example of Interrupt Handling Routine
Start of IRQ level-sense or IRL
for the INTC to respond to
level interrupt) handling
address in the local bus
cancellation requests
End of IRQ/IRL level
Interrupt handling
interrupt handling
1) Writing to the GPIO register or local
2) Read the address of writing.
Allow at least 8 bus-clock cycles for
cancellation and the INTC response
time.
1) Set the corresponding bit in
2) Set the corresponding bit in
3) Read INTMSK0/1.
bus space.
INTMSK0/1 to 1.
INTMSKCLR0/1 to 1.