R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 14

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Caches................................................................................................ 197
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Section 9 L Memory.......................................................................................... 227
9.1
9.2
Rev.1.00 Dec. 13, 2005 Page xii of l
7.7.5
7.7.6
Features.............................................................................................................................. 197
Register Descriptions......................................................................................................... 200
8.2.1
8.2.2
8.2.3
8.2.4
Operand Cache Operation.................................................................................................. 207
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Instruction Cache Operation .............................................................................................. 212
8.4.1
8.4.2
8.4.3
Cache Operation Instruction .............................................................................................. 214
8.5.1
8.5.2
Memory-Mapped Cache Configuration ............................................................................. 216
8.6.1
8.6.2
8.6.3
8.6.4
Store Queues ...................................................................................................................... 223
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
Notes on Using 32-Bit Address Extended Mode ............................................................... 226
Features.............................................................................................................................. 227
Register Descriptions......................................................................................................... 228
Memory-Mapped PMB Configuration.................................................................. 192
Notes on Using 32-Bit Address Extended Mode .................................................. 194
Cache Control Register (CCR) ............................................................................. 201
Queue Address Control Register 0 (QACR0)....................................................... 203
Queue Address Control Register 1 (QACR1)....................................................... 204
On-Chip Memory Control Register (RAMCR) .................................................... 205
Read Operation ..................................................................................................... 207
Prefetch Operation ................................................................................................ 208
Write Operation .................................................................................................... 209
Write-Back Buffer ................................................................................................ 211
Write-Through Buffer........................................................................................... 211
OC Two-Way Mode ............................................................................................. 211
Read Operation ..................................................................................................... 212
Prefetch Operation ................................................................................................ 213
IC Two-Way Mode............................................................................................... 213
Coherency between Cache and External Memory ................................................ 214
Prefetch Operation ................................................................................................ 215
IC Address Array.................................................................................................. 217
IC Data Array ....................................................................................................... 219
OC Address Array ................................................................................................ 220
OC Data Array...................................................................................................... 222
SQ Configuration.................................................................................................. 223
Writing to SQ........................................................................................................ 223
Transfer to External Memory ............................................................................... 224
Determination of SQ Access Exception................................................................ 225
Reading from SQ .................................................................................................. 225