R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 469

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
63 to 3
2 to 0
Bit Name

SMS
Initial
Value
All 0
000
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SDRAM Mode Select
These bits initialize the DDR-SDRAM when power is
supplied and after release of the reset signal. Software
can be used to set these bits as listed below so that the
corresponding command is issued.For details on the
initialization procedure, see section 12.5.2, DDR-
SDRAM Initialization Sequence. After the DDR-
SDRAM has been initialized, normal operation (000) is
specified.
000: Normal operation
001: A NOP command is issued (only valid if the DCE
010: A PREALL command is issued (only valid if the
011: The CKE pin is enabled. At that time, the
100: The REFA (auto-refresh) command is issued (only
Settings other than the above are prohibited. If such
settings are made, correct operation is not guaranteed.
Note that the PCKE bit in MIM is used to set the CKE
pin low for reduced power consumption of the DDR-
SDRAM.
bit in MIM is set to 1).
DCE bit in MIM is set to 1).
DESELECT command is issued (only valid if the
DCE bit in MIM is set to 1).
valid if the DCE bit in MIM is set to 1).
Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 417 of 1286
REJ09B0158-0100