R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 15

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.3
9.4
9.5
9.6
Section 10 Interrupt Controller (INTC) .............................................................243
10.1 Features.............................................................................................................................. 243
10.2 Input/Output Pins ............................................................................................................... 250
10.3 Register Descriptions ......................................................................................................... 251
10.4 Interrupt Sources................................................................................................................ 296
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Operation ........................................................................................................................... 238
9.3.1
9.3.2
9.3.3
L Memory Protective Functions ........................................................................................ 240
Usage Notes ....................................................................................................................... 241
9.5.1
9.5.2
9.5.3
Note on Using 32-Bit Address Extended Mode................................................................. 241
10.1.1 Interrupt Method ................................................................................................... 245
10.1.2 Interrupt Types in INTC ....................................................................................... 246
10.3.1 Interrupt Control Register 0 (ICR0)...................................................................... 255
10.3.2 Interrupt Control Register 1 (ICR1)...................................................................... 258
10.3.3 Interrupt Priority Register (INTPRI)..................................................................... 259
10.3.4 Interrupt Source Register (INTREQ).................................................................... 260
10.3.5 Interrupt Mask Registers (INTMSK0 to INTMSK2)............................................ 261
10.3.6 Interrupt Mask Clear Registers (INTMSKCLR0 to INTMSKCLR2)................... 266
10.3.7 NMI Flag Control Register (NMIFCR) ................................................................ 271
10.3.8 User Interrupt Mask Level Register (USERIMASK) ........................................... 273
10.3.9 On-chip Module Interrupt Priority Registers (INT2PRI0 to INT2PRI7).............. 276
10.3.10 Interrupt Source Register (INT2A0: Not affected by Mask States) ...................... 277
10.3.11 Interrupt Source Register (INT2A1: Affected by Mask States)............................ 280
10.3.12 Interrupt Mask Register (INT2MSKR)................................................................. 282
10.3.13 Interrupt Mask Clear Register (INT2MSKCR)..................................................... 285
10.3.14 On-chip Module Interrupt Source Registers (INT2B0 to INT2B7) ...................... 287
10.3.15 GPIO Interrupt Set Register (INT2GPIC)............................................................. 294
10.4.1 NMI Interrupt........................................................................................................ 296
10.4.2 IRQ Interrupts ....................................................................................................... 296
On-Chip Memory Control Register (RAMCR) .................................................... 229
L Memory Transfer Source Address Register 0 (LSA0) ...................................... 230
L Memory Transfer Source Address Register 1 (LSA1) ...................................... 232
L Memory Transfer Destination Address Register 0 (LDA0) .............................. 234
L Memory Transfer Destination Address Register 1 (LDA1) .............................. 236
Access from the CPU and FPU............................................................................. 238
Access from the SuperHyway Bus Master Module .............................................. 238
Block Transfer ...................................................................................................... 238
Page Conflict ........................................................................................................ 241
L Memory Coherency ........................................................................................... 241
Sleep Mode ........................................................................................................... 241
Rev.1.00 Dec. 13, 2005 Page xiii of l