R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 665
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The CPG generates clocks provided to both the inside and outside of the SH7780, and controls the
power-down mode function. The CPG comprises a crystal oscillator circuit, PLLs, and a divider.
15.1
The CPG has the following features.
• Generates SH7780 internal clocks
• Generates SH7780 external bus clocks.
• Selects two clock modes
• Changes frequencies
• Provides the clock stop and module standby functions in control sleep mode
SH7780 internal clocks are: the CPU clock (Ick) which is used in the CPU, FPU, cache, and
TLB; the SHwy clock (SHck) which is used by the SuperHyway bus; and peripheral clocks
(Pck) which are used to interface with on-chip peripheral modules.
SH7780 external bus clocks are the bus clock (Bck) which is used to interface with the external
devices and memory clocks (DDRck) which are used in the DDRIF.
Selects a crystal resonator or an externally input clock as the CPG clock input.
Changes frequencies of the internal clocks by the divider in the CPG. The divider is controlled
with the frequency control register (FRQCR) set by software.
Control sleep mode is the CPU stop mode. In control module standby mode, specific modules
can be stopped.
Features
Section 15 Clock Pulse Generator (CPG)
Rev.1.00 Dec. 13, 2005 Page 613 of 1286
Section 15 Clock Pulse Generator (CPG)
REJ09B0158-0100
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