R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 471
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
17, 16
15 to 13 SRFC
12
11
Bit Name
SWR
RW
SRRD
Initial
Value
00
000
0
0
R/W
R/W
R/W
R/W
R/W
Description
Minimum Number of Cycles from Read Command to
Write Command
These bits specify the minimum number of cycles
required by the SRAM from the issuing of a READ
command to the issuing of a subsequent WRITE
command.
00: 3 cycles
01: 4 cycles
10: 5 cycles
11: 6 cycles
Number of Cycles within a Single Individual Bank
These bits specify the number of cycles between the
following access operations in a given bank (the
corresponding time is tRFC).
(1) From auto-refresh to issuing the ACT command
(2) From auto refresh to auto refresh
000: 11 cycles
001: 12 cycles
010: 13 cycles
011: 14 cycles
100: 15 cycles
Other than above: Setting prohibited
PRE/PREALL Command Issuing Cycle
Within write cycles, specifies the number of cycles from
the last postamble to the issuing of a PRE/PREALL
command (the corresponding time is tWR).
0: 2 cycles
1: 3 cycles
Inter-bank Number of Cycles between ACT Commands
Specifies the minimum number of cycles between the
issuing of ACT commands (the corresponding time is
tRRD) for any two banks.
0: 2 cycles
1: 3 cycles
Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 419 of 1286
REJ09B0158-0100
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