R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 545
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(7)
This register is the mask register for PCIIR.
Initial value:
Initial value:
Bit
31 to 15
14
13 to 10
9
8
7
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Interrupt Mask Register (PCIIMR)
Bit:
Bit:
Bit Name
TTADIM
TMTOIM
MDEIM
APEDIM
31
15
—
—
R
R
R
R
0
0
R/W
TTA
DIM
30
14
—
R
R
R
0
0
Initial
Value
All 0
0
All 0
0
0
0
29
13
—
—
R
R
R
R
0
0
28
12
—
—
R
R
R
R
0
0
R/W
SH: R
PCI: R
SH: R/W
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
27
11
—
—
R
R
R
R
0
0
26
10
—
—
R
R
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Target-Abort Interrupt Mask
0: PCIIR.TTADI disabled (masked)
1: PCIIR.TTADI enabled (not masked)
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Retry Time Out Interrupt Mask
0: PCIIR.TMTOI disabled (masked)
1: PCIIR. TMTOI enabled (not masked)
Master Function Disable Error Interrupt Mask
0: PCIIR.MDEI disabled (masked)
1: PCIIR.MDEI enabled (not masked)
Address Parity Error Detection Interrupt Mask
0: PCIIR.APEDI disabled (masked)
1: PCIIR.APEDI enabled (not masked)
R/W
TMT
OIM
25
—
R
R
R
0
9
0
R/W
MDE
24
—
IM
R
R
R
0
8
0
APE
R/W
DIM
23
—
R
R
R
0
7
0
Rev.1.00 Dec. 13, 2005 Page 493 of 1286
R/W
DIM
SE
22
—
R
R
R
0
6
0
DPEI
TWM
R/W
21
—
R
R
R
0
5
0
Section 13 PCI Controller (PCIC)
DPEI
TRM
R/W
20
—
R
R
R
0
4
0
TAD
IMM
R/W
19
—
R
R
R
0
3
0
REJ09B0158-0100
MAD
IMM
R/W
18
—
R
R
R
0
2
0
PDIM
R/W
MW
17
—
R
R
R
0
1
0
PEIM
MRD
R/W
16
—
R
R
R
0
0
0
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