R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 197

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 6 Floating-Point Unit (FPU)
• Matrix (4 × 4) × matrix (4 × 4):
This operation requires the execution of four FTRV instructions.
Since an inexact exception is not detected by an FIRV instruction, the inexact exception (I) bit in
both the FPU exception cause field and flag field are always set to 1 when an FTRV instruction is
executed. Therefore, if the I bit is set in the FPU exception enable field, FPU exception handling
will be executed. It is not possible to check all data types in the registers beforehand when
executing an FTRV instruction. If the V bit is set in the FPU exception enable field, FPU
exception handling will be executed.
FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is
executed, matrix elements must be set in an array in the background bank. However, to create the
actual elements of a translation matrix, it is easier to use registers in the foreground bank. When
the LDS instruction is used on FPSCR, this instruction takes four to five cycles in order to
maintain the FPU state. With the FRCHG instruction, the FR bit in FPSCR can be changed in one
cycle.
6.6.2
Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, the SH-4A also supports high-
speed data transfer instructions.
When the SZ bit is 1, the SH-4A can perform data transfer by means of pair single-precision data
transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
• FSCHG
This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use
and non-use of pair single-precision data transfer.
Rev.1.00 Dec. 13, 2005 Page 145 of 1286
REJ09B0158-0100