R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 650
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 650 of 1342
- Download datasheet (7Mb)
Section 14 Direct Memory Access Controller (DMAC)
Rev.1.00 Dec. 13, 2005 Page 598 of 1286
REJ09B0158-0100
Intermittent mode 16 (DMAOR.CMS = 10, CHCR.LCKN = 0 or 1, CHCR.TB = 0),
Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode
DREQ
SuperHyway
bus cycle
intermittent mode 64 (DMAOR.CMS = 11, CHCR.LCKN = 0 or 1, CHCR.TB = 0)
In intermittent mode of cycle steal, the DMAC returns the SuperHyway bus mastership to
other bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte
unit) is complete. If the next transfer request occurs after that, the DMAC issues the next
transfer request after waiting for 16 or 64 clocks in Bck count, and obtains the bus
mastership from other bus master. The DMAC then transfers data of one-transfer unit and
returns the bus mastership to other bus master. These operations are repeated until the
transfer end condition is satisfied. It is thus possible to make lower the ratio of bus
occupation by DMA transfer than cycle-steal normal mode.
When the DMAC issues again the transfer request, DMA transfer can be postponed in case
of entry updating due to cache miss.
The intermittent modes, however, must be cycle steal mode in all channels 0 to 5 or 6 to11
for the corresponding transfer channel.
Figure 14.8 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2
DREQ
SuperHyway
bus cycle
CPU
CPU
CPU
CPU
(DREQ Low Level Detection)
(DREQ Low Level Detection)
CPU
CPU
DMAC
Read
Bus mastership retured to CPU once
DMAC DMAC CPU
Read/Write
CPU
More than 16 or 64 Bck
DMAC
Write
CPU
CPU DMAC DMAC CPU
DMAC
Read
Read/Write
CPU
DMAC
Write
CPU
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