R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 295

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The interrupt controller (INTC) determines the priority of interrupt sources and controls the flow
of interrupt requests to the CPU (SH-4A). The INTC has registers for setting the priority of each
of the interrupts and processing of interrupt requests follows the priority order set in these registers
by the user.
10.1
SH-4 compatible specifications
• Fifteen levels of external interrupt priority can be set
• NMI noise canceler function
• NMI request masking when the block bit (BL) in the status register (SR) is set to 1
Extended functions for the SH-4A
• Automatically updates the IMASK bit in SR according to the accepted interrupt level
• Thirty priority levels for interrupts from on-chip modules
• User-mode interrupt disabling function
Figure 10.1 shows a block diagram of the INTC.
By setting the interrupt priority registers, the priorities of external interrupts can be selected
from 15 levels for individual request sources.
An NMI input-level bit indicates the NMI pin state. The bit can be read within the interrupt
exception handling routine to confirm the pin state and thus achieve a form of noise
cancellation.
Masking or non-masking of NMI requests when the BL bit in SR is set to 1 can be selected.
By setting the interrupt priority registers (INT2PRI0 to INT2PRI7) for the on-chip module
interrupts, any of 30 priority levels can be assigned to the individual requesting sources.
An interrupt mask level in the user interrupt mask level register (USERIMASK) can be
specified to disable interrupts which do not have higher priority than the specified mask level.
This setting can be made in user mode.
Features
Section 10 Interrupt Controller (INTC)
Rev.1.00 Dec. 13, 2005 Page 243 of 1286
Section 10 Interrupt Controller (INTC)
REJ09B0158-0100