R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 194

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 6 Floating-Point Unit (FPU)
6.5
6.5.1
FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1.
When the FPU instruction is in other than delayed slot, the general FPU disable exception is
occurred. When the FPU instruction is in the delay slot, the slot FPU disable exception is
occurred.
6.5.2
The exception sources are as follows:
• FPU error (E): When FPSCR.DN = 0 and a denormalized number is input
• Invalid operation (V): In case of an invalid operation, such as NaN input
• Division by zero (Z): Division with a zero divisor
• Overflow (O): When the operation result overflows
• Underflow (U): When the operation result underflows
• Inexact exception (I): When overflow, underflow, or rounding occurs
The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V,
Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding
to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled.
When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1,
and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception
does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the
corresponding bit in the FPU exception flag field remains unchanged.
6.5.3
FPU exception handling is initiated in the following cases:
• FPU error (E): FPSCR.DN = 0 and a denormalized number is input
• Invalid operation (V): FPSCR.Enable.V = 1 and (instruction = FTRV or invalid operation)
• Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor or the input of
• Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result
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REJ09B0158-0100
FSRRA is zero
overflow
Floating-Point Exceptions
General FPU Disable Exceptions and Slot FPU Disable Exceptions
FPU Exception Sources
FPU Exception Handling