R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 464

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 DDR-SDRAM Interface (DDRIF)
12.4.1
Rev.1.00 Dec. 13, 2005 Page 412 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Initial value:
Initial value:
Bit
63 to 48 
47, 46
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Memory Interface Mode Register (MIM)
Bit Name
BOMODE
Note: * Depends on the setting of external pin (MODE5).
R/W
63
47
BOMODE
31
15


—
R
R
R
0
0
0
R/W
62
46
30
14


—
R
R
R
0
0
0
LOCK
61
45
29
13



—
R
R
R
R
0
0
0
Initial
Value
All 0
00
R/W
R/W
PC
KE
60
44
28
12

—
R
R
0
0
0
R/W
R/W
R
R/W
59

43

27
11

R
R
R
0
0
1
0
R/W
58
42
26
10



R
R
R
0
0
1
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Access Mode Switch
Switch access modes for the DDR-SDRAM.
The DDRIF supports two SDRAM access modes. For
details on operation in each of the modes, see section
12.5.4, SDRAM Access Mode.
00: Bank open mode
01: Bank closed mode
Other than above: Setting prohibited
DRE
R/W
R/W
57
41
25


R
R
0
0
0
9
0
R/W
END
IAN
56
40
24


—
R
R
R
0
0
0
8
*
R/W
R/W
BW
55
39
23


R
R
0
0
0
7
0
R/W
DRI
54
38
22



R
R
R
0
0
0
6
0
R/W
53
37
21



R
R
R
0
0
1
5
0
R/W
52
36
20



R
R
R
0
0
1
4
0
DLLEN
R/W
R/W
51

35

19
R
R
0
0
0
3
0
R/W
SEL
50
34
18

FS

R
R
R
0
0
1
2
0
R/W
R/W
ODE
RM
49
33
17


R
R
0
0
0
1
0
DCE
R/W
R/W
47
32
16


R
R
0
0
0
0
0