R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 686
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 686 of 1342
- Download datasheet (7Mb)
Section 16 Watchdog Timer and Reset
16.4.2
1. Set the WDTCNT overflow interval value in WDTST.
2. Set the WT/IT bit in WDTCSR to 1, select the type of reset with the RSTS bit.
3. When the TME bit in WTCSR is set to 1, the WDT count starts.
4. During operation in watchdog timer mode, clear to the WDTCNT or WDTBCNT periodically
5. When the WDTCNT overflows, the WDT sets the WOVF flag in WDTCSR to 1, and
16.4.3
When the WDT is operating in interval timer mode, an interval timer interrupt is generated each
time the counter overflows. This enables interrupts to be generated at fixed intervals.
1. Set the WDTCNT overflow time in WDTST.
2. Clear the WT/IT bit in WDTCSR to 0.
3. When the TME bit in WDTCSR is set to 1, the WDT count starts.
4. When the WDTCNT overflows, the WDT sets the IOVF flag in WDTCSR to 1, and sends an
Rev.1.00 Dec. 13, 2005 Page 634 of 1286
REJ09B0158-0100
so that WDTCNT does not overflow. See section 16.4.5, Clearing WDT Counter for WDT
counter clear method.
generates a reset of the type specified by the RSTS bit. After reset operation, the WDTCNT
and WDTBCNT continues counting again.
interval timer interrupt (ITI) request to INTC. The counter continues counting.
Manual_reset()
{
}
Using watchdog timer mode
Using Interval timer mode
EXPEVT = H'0000 0020;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A000 0000;
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