R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 334

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
10.3.12 Interrupt Mask Register (INT2MSKR)
INT2MSKR is a 32-bit readable/writable register that sets interrupt masking for each of the
sources indicated in the interrupt source register. The CPU is not notified of interrupts for which
the corresponding bits in INT2MSKRG are set to 1.
INT2MSKR is initialized to H'FFFF FFFF (mask state) by a reset.
Table 10.8 shows the correspondence between bits in INT2MSKR and interrupt masking.
Rev.1.00 Dec. 13, 2005 Page 282 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
2
1
0
R/W:
R/W:
Initial
Value R/W Source
0
0
0
Bit:
Bit:
R/W
31
15

R
1
1
R
R
R
R/W
30
14

R
1
1
RTC
TMU
channels
3 to 5
TMU
channels
0 to 2
R/W
29
13

R
1
1
R/W
28
12

R
1
1
Function
Indicates the RTC interrupt
source
Indicates the TMU channel 3
to 5 interrupt source
Indicates the TMU channel 0
to 2 interrupt source
27

11

R
R
1
1
26
10


R
R
1
1
R/W
R/W
25
1
9
1
R/W
R/W
24
1
8
1
R/W
R/W
23
1
7
1
R/W
22

R
1
6
1
Description
Indicates interrupt sources for the
individual peripheral modules
(INT2A1 is affected by the state of
the interrupt mask register).
0: No interrupt
1: An interrupt has been
Note: Interrupt sources can also
R/W
R/W
generated
21
1
5
1
be identified by directly
reading the INTEVT code
that is sent to the CPU. In
this case, reading INT2A0
is not necessary.
R/W
R/W
20
1
4
1
R/W
R/W
19
1
3
1
R/W
R/W
18
1
2
1
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1