R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 311

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note: When an IRQ pin is set for level input (IRQnS1 = 1), the interrupt source is held until the
10.3.3
INTPRI is a 32-bit readable/writable register used to set the priorities of IRQ[7:0] (as levels from
15 to 0). These settings are only valid for IRQ/IRL7 to IRQ/IRL4 or IRQ/IRL3 to IRQ/IRL0 when
set up as individual IRQ interrupts by setting the IRLM0 or IRLM1 bit in ICR0 to 1.
Interrupt priorities should be established by setting values from H'F to H'1 in each of the 4-bit
fields. A larger value corresponds to a higher priority. When the value H'0 is set in a field, the
corresponding interrupt is masked (initial value).
Initial value:
Initial value:
Bit
31 to 28
27 to 24
23 to 20
19 to 16
15 to 12
11 to 8
7 to 4
3 to 0
R/W:
R/W:
Bit:
Bit:
CPU accepts the interrupt (this is also true for other interrupts). Therefore, even if an
interrupt source is disabled before this LSI returns from sleep mode, branching of
processing to the interrupt handler when this LSI returns from sleep mode is guaranteed. A
held interrupt can be cleared by setting the corresponding interrupt mask bit (the IM bit in
the interrupt mask register) to 1.
Interrupt Priority Register (INTPRI)
Name
IP0
IP1
IP2
IP3
IP4
IP5
IP6
IP7
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
Initial
Value
H'0
H'0
H'0
H'0
H'0
H'0
H'0
H'0
IP0
IP4
R/W
R/W
29
13
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
Description
Set the priority of IRQ0 as an individual pin interrupt request.
Set the priority of IRQ1 as an individual pin interrupt request.
Set the priority of IRQ2 as an individual pin interrupt request.
Set the priority of IRQ3 as an individual pin interrupt request.
Set the priority of IRQ4 as an individual pin interrupt request.
Set the priority of IRQ5 as an individual pin interrupt request.
Set the priority of IRQ6 as an individual pin interrupt request.
Set the priority of IRQ7 as an individual pin interrupt request.
R/W
R/W
26
10
0
0
IP5
IP1
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
Rev.1.00 Dec. 13, 2005 Page 259 of 1286
R/W
R/W
22
0
6
0
IP6
IP2
Section 10 Interrupt Controller (INTC)
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0158-0100
R/W
R/W
18
0
2
0
IP3
IP7
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0