R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 47

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 11.10
Table 11.11
Table 11.12
Table 11.13
Table 11.14
Table 11.15
Table 11.16
Section 12 DDR-SDRAM Interface (DDRIF)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Section 13 PCI Controller (PCIC)
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.7
Table 14.8
Table 14.9
Table 14.10
Table 14.11
Table 14.12
Table 14.13
Table 14.14
Pin Configuration.................................................................................................. 403
Access and Data Alignment in Little Endian Mode.............................................. 406
Access and Data Alignment in Big Endian Mode................................................. 408
Register Configuration.......................................................................................... 410
Register States in Each Operating Mode .............................................................. 411
SDRAM Commands Issuable by DDRIF ............................................................. 426
Relationship between SPLIT Bits and Address Multiplexing............................... 429
Input/Output Pins.................................................................................................. 446
List of PCIC Registers .......................................................................................... 449
Register States in Each Operating Mode .............................................................. 452
Supported Bus Commands.................................................................................... 522
PCIC Address Map ............................................................................................... 524
Interrupt Priority ................................................................................................... 543
Pin Configuration.................................................................................................. 559
Register Configuration of DMAC......................................................................... 561
Register States in Each Processing Mode ............................................................. 564
Transfer Request Sources ..................................................................................... 587
Selecting External Request Detection with DL, DS Bits ...................................... 589
Selecting External Request Detection with DO Bit .............................................. 589
Peripheral Module Request Modes ....................................................................... 591
DMA Transfer Matrix in Auto-Request Mode (all channels)............................... 599
DMA Transfer Matrix in External Request Mode (only channels 0 to 3)............. 600
16-Bit External Device/Big-Endian Access and Data Alignment..................... 353
8-Bit External Device/Big-Endian Access and Data Alignment....................... 354
32-Bit External Device/Little-Endian Access and Data Alignment.................. 355
16-Bit External Device/Little-Endian Access and Data Alignment.................. 355
8-Bit External Device/Little-Endian Access and Data Alignment.................... 356
Relationship between Address and CE When Using PCMCIA Interface ......... 375
Relationship between D31 to D29 and Access Size in Address Phase ............. 383
DMA Transfer Matrix in Peripheral module Request Mode ............................ 601
Register Settings for SRAM, Burst ROM, Byte Control SRAM Interface....... 611
Register Settings for PCMCIA Interface .......................................................... 612
Register Settings for MPX Interface (Read Access)......................................... 612
Register Settings for MPX Interface (Write Access) ........................................ 612
Rev.1.00 Dec. 13, 2005 Page xlv of l