R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 337

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.3.13 Interrupt Mask Clear Register (INT2MSKCR)
INT2MSKCR is a 32-bit write-only register used to clear mask settings in the interrupt mask
register. Setting a bit in this register to 1 clears the masking of the corresponding interrupt source.
The bits of this register are always read as 0.
Table 10.9 shows the correspondence between bits in INT2MSKCR and interrupt mask clearing.
Table 10.9 Correspondence between Bits in INT2MSKCR and Interrupt Mask Clearing
Initial value:
Initial value:
Bit
31 to
26
25
24
23
22
21
20
19
18
17
R/W:
R/W:
Initial
Value R/W Target
All 0
0
0
0
0
0
0
0
0
0
Bit:
Bit:
R/W
31
15

R
0
0
R
R/W GPIO
R/W FLCTL
R/W SSI
R/W MMCIF
R/W HSPI
R/W SIOF
R/W PCIC (5)
R/W PCIC (4)
R/W PCIC (3)
R/W
30
14

R
0
0
(Reserved)
R/W
29
13

R
0
0
R/W
28
12

R
0
0
27
11


R
R
0
0
Function
These bits are always read as 0.
The write value should always be
0.
Clears the GPIO interrupt masking
Clears the FLCTL interrupt
masking
Clears the SSI interrupt masking
Clears the MMC interrupt masking
Clears the HSPI interrupt masking
Clears the SIOF interrupt masking
Clears the PCIERR and PCIPWD3
to PCIPWD0 interrupts masking
Clears the PCIINTD interrupt
masking
Clears the PCIINTC interrupt
masking
26
10


R
R
0
0
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
Rev.1.00 Dec. 13, 2005 Page 285 of 1286
R/W
22

R
0
6
0
Section 10 Interrupt Controller (INTC)
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
Description
Clears interrupt
masking for individual
modules.
[When reading]
Always 0
[When writing]
0: Invalid
1: Interrupt mask is
cleared
R/W
R/W
19
0
3
0
REJ09B0158-0100
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0