R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 624

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
14.3.7
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Rev.1.00 Dec. 13, 2005 Page 572 of 1286
REJ09B0158-0100
Bit
31
30
29, 28
Initial value:
Initial value:
Note: * Writing 0 is possible to clear the flag.
R/W:
R/W:
Bit:
Bit:
DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11)
Bit Name
—
LCKN
—
R/W
31
15
R
0
0
DM[1:0]
LCKN
R/W
R/W
30
14
1
0
R/W
29
13
Initial
Value
0
1
All 0
R
0
0
SM[1:0]
R/W
28
12
R
0
0
R/W
R/W
R/W
R
R/W
R
27
11
0
0
RPT[2:0]
R/W
R/W
26
10
0
0
RS[3:0]
Descriptions
Reserved
This bit is always read as 0. The write value should
always be 0.
Bus Lock Signal Disable
Specifies whether enable or disable the bus lock signal
output when a read instruction for the SuperHyway bus.
This bit is effective in cycle steal mode, and should be
cleared to 0 in burst mode.
To disable the bus lock signal, the bus request from the
bus master other than the DMAC could be received,
and so improve the bus usage efficiency.
0: Bus lock signal output enabled
1: Bus lock signal output disabled
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
R/W
25
0
9
0
R/W
24
R
0
8
0
R/W
R/W
DO
23
DL
0
7
0
R/W
R/W
DS
22
RL
0
6
0
R/W
TB
21
R
0
5
0
R/W R/(W)* R/W
R/W
TS2
20
0
4
0
TS[1:0]
R/W
HE
19
0
3
0
R/W R/(W)*
HIE
18
IE
0
2
0
R/W
AM
17
TE
0
1
0
R/W
R/W
DE
16
AL
0
0
0