R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1195

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

30.4.4
SDBSR is a shift register, located on the PAD, for controlling the input/Output pins, which
supports the boundary scan mode of the JTAG standard. Using the EXTEST and
SAMPLE/PRELOAD commands, a boundary-scan test complying with the JTAG standards
(IEEE1149.1) can be carried out. Table 30.6 shows the correspondence between pins of this LSI
and the SDBSR values.
This register cannot be accessed from the CPU regardless of the LSI mode. This register is not
initialized by a power-on reset and the TRST pin asserted.
Table 30.6 SDBSR Configuration
Number
524
523
522
521
520
519
518
517
516
515
514
513
512
511
510
509
508
507
506
505
504
Boundary Scan Register (SDBSR)
Pin Name
From TDI
DACK3/IRQOUT/AUDATA3
DACK3/IRQOUT/AUDATA3
DACK3/IRQOUT/AUDATA3
DACK2/MRESETOUT/AUDATA2
DACK2/MRESETOUT/AUDATA2
DACK2/MRESETOUT/AUDATA2
DACK1/MODE1
DACK1/MODE1
DACK1/MODE1
DACK0/MODE0
DACK0/MODE0
DACK0/MODE0
DREQ3/INTC/AUDATA1
DREQ3/INTC/AUDATA1
DREQ3/INTC/AUDATA1
DREQ2/INTB/AUDATA0
DREQ2/INTB/AUDATA0
DREQ2/INTB/AUDATA0
DREQ1
DREQ1
DREQ1
Output
Output
Input
Output
Input
I/O*
Control
Input
Output
Control
Input
Control
Control
Output
Control
Input
Output
Control
Input
Output
Control
Input
Number
503
502
501
500
499
498
497
496
495
494
493
492
491
490
489
488
487
486
485
484
483
482
Section 30 User Debugging Interface (H-UDI)
Rev.1.00 Dec. 13, 2005 Page 1143 of 1286
Pin Name
DREQ0
DREQ0
DREQ0
DRAK3/CE2B/AUDSYNC
DRAK3/CE2B/AUDSYNC
DRAK3/CE2B/AUDSYNC
DRAK2/CE2A/AUDCK
DRAK2/CE2A/AUDCK
DRAK2/CE2A/AUDCK
DRAK1/MODE7
DRAK1/MODE7
DRAK1/MODE7
DRAK0/MODE2
DRAK0/MODE2
DRAK0/MODE2
A25
A25
A25
STATUS0/CMT_CTR0
STATUS0/CMT_CTR0
STATUS0/CMT_CTR0
STATUS1/CMT_CTR1
REJ09B0158-0100
I/O*
Output
Control
Input
Output
Control
Input
Output
Control
Input
Output
Control
Input
Output
Control
Input
Output
Control
Input
Output
Control
Input
Output