R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1103

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Set DMAC related registers (example of channel 0, 1)
1. DMA source address registers (SAR0, SAR1)
2. DMA destination address registers (DAR0, DAR1)
3. DMA transfer count registers (TCR0, TCR1)
4. DMA channel control registers (CHCR0, CHCR1)
5. DMA extended resource selector (DMARS0)
Set DMA operation register (DMAOR0)
DME = 1 (enable channel 0 to 5 transfer)
Set common control register (FLCMNCR)
ACM [1:0] = 01 (sector access mode)
CE0 = 1 (chip enable)
TYPESEL = 1 (NAND flash memory)
Specify ECC position to ECCPOS [1:0]
Set command control register (FLCMDCR)
SELRW = 1 (flash write)
DOCMD1 = 1 (perform first command stage)
DOCMD2 = 1 (perform second command stage)
DOADR = 1 (perform address stage)
ADRMD = 1 (specify sector access address)
ADRCNT [1:0] = 10 (issue 3-byte address)
DOSR = 1 (perform status read)
Specify number of sector transfer to SCTCNT [15:0]
Set command code register (FLCMCDR)
CMD [7:0] = H'80 (flash write command)
CMD [15:8] = H'10 (flash write execute command)
SAR0 [31:0]: set start address of writing data
SAR1 [31:0]: set start address of writing control code
DAR0 [31:0]: set FLDTFIFO address
DAR1 [31:0]: set FLECFIFO address
TCR0 [31:0] = H'0000 0080 (512 bytes = 4 x 128)
TCR1 [31:0] = H'0000 0004 (16 bytes = 4 x 4)
SM [1:0] = 01 (source address is incremented)
RS [3:0] = 1000 (on-chip peripheral module request)
TS [2:0] = 010 (longword)
DE = 1 (DMA transfer enable)
DMARS0 [15:0] = H'8783 (FLCTL control code and
data part transmit and receive)
Figure 27.9 NAND Flash Sector Access (Flash Write) Using DMA
Sector access (Flash Write)
Set address register (FLADR)
Specify physical sector address to ADR [17:0]
Set interrupt DMA control register (FLINTDMACR)
DREQ1EN = 1
(enable DMA transfer request from FLECFIFO)
DREQ0EN = 1
(enable DMA transfer request from FLDTFIFO)
Set transfer control register (FLTRCR)
TRSTRT = 1 (transfer start)
Set Interrupt DMA Control Register (FLINTDMACR)
DREQ1EN = 1
(enable DMA transfer request from FLECFIFO)
DREQ0EN = 1
(enable DMA transfer request from FLDTFIFO)
End of flash memory access
FLTRCR.TREND = 0 (clear processing end flag)
Read status
Check FLBSYCNT.STAT [7:0]
Section 27 NAND Flash Memory Controller (FLCTL)
Perform flash memory writing
Issue first command
Issue address
Data stage (sector access)
Issue second command
Read status
Rev.1.00 Dec. 13, 2005 Page 1051 of 1286
FLTRCR.TREND = 1?
END
Yes
REJ09B0158-0100
No