R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 817

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
6
5
4
3
Bit Name
RTSDT*
CTSIO*
CTSDT*
SCKIO
Initial
Value
—
0
—
0
R/W
R/W
R/W
R/W
R/W
Description
Serial Port SCIF0_RTS Port Data
Specifies the serial port SCIF0_RTS pin input/output
data. Input or output is specified by the RTSIO bit. In
output mode, the RTSDT bit value is output to the
SCIF0_RTS pin. The SCIF0_RTS pin value is read
from the RTSDT bit regardless of the value of the
RTSIO bit. The initial value of this bit after a power-on
reset or manual reset is undefined.
0: Input/output data is low-level
1: Input/output data is high-level
Serial Port SCIF0_CTS Port Input/Output
Specifies the serial port SCIF0_CTS pin input/output
condition. When actually setting the SCIF0_CTS pin as
a port output pin to output the value set by the CTSDT
bit, the MCE bit in SCFCR should be cleared to 0.
0: CTSDT bit value is not output to SCIF0_CTS pin
1: CTSDT bit value is output to SCIF0_CTS pin
Serial Port SCIF0_CTS Port Data
Specifies the serial port SCIF0_CTS pin input/output
data. Input or output is specified by the CTSIO bit. In
output mode, the CTSDT bit value is output to the
SCIF0_CTS pin. The SCIF0_CTS pin value is read
from the CTSDT bit regardless of the value of the
CTSIO bit. The initial value of this bit after a power-on
reset or manual reset is undefined.
0: Input/output data is low-level
1: Input/output data is high-level
Serial Port Clock Port Input/Output
Specifies the serial port SCIF_SCK pin input/output
condition. When actually setting the SCIF_SCK pin as
a port output pin to output the value set by the SCKDT
bit, the CKE1 and CKE0 bits in SCSCR should be
cleared to 0.
0: SCKDT bit value is not output to SCIF_SCK pin
1: SCKDT bit value is output to SCIF_SCK pin
Section 21 Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Dec. 13, 2005 Page 765 of 1286
REJ09B0158-0100