R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 228
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Memory Management Unit (MMU)
7.4.5
When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The
problem is that, when a number of virtual addresses are mapped onto a single physical address, the
same physical address data is recorded in a number of cache entries, and it becomes impossible to
guarantee data integrity. This problem does not occur with the instruction TLB and instruction
cache because data is only read in these cases. In this LSI, entry specification is performed using
bits 12 to 5 of the virtual address in order to achieve fast operand cache operation. However, bits
12 to 10 of the virtual address in the case of a 1-Kbyte page, and bit 12 of the virtual address in the
case of a 4-Kbyte page, are subject to address translation. As a result, bits 12 to 10 of the physical
address after translation may differ from bits 12 to 10 of the virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in UTLB entries.
• When address translation information whereby a number of 1-Kbyte page UTLB entries are
• When address translation information whereby a number of 4-Kbyte page UTLB entries are
• Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different
• Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different
The above restrictions apply only when performing accesses using the cache.
Note: When multiple items of address translation information use the same physical memory to
Rev.1.00 Dec. 13, 2005 Page 176 of 1286
REJ09B0158-0100
translated into the same physical address is recorded in the UTLB, ensure that the VPN[12:10]
values are the same.
translated into the same physical address is recorded in the UTLB, ensure that the VPN[12]
value is the same.
page size.
page size.
provide for future expansion of the SuperH RISC engine family, ensure that the
VPN[20:10] values are the same. Also, do not use the same physical address for address
translation information of different page sizes.
Avoiding Synonym Problems
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