R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 353

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.4.6
Table 10.12 lists the codes for the interrupt event register (INTEVT) and the order of interrupt
priority.
Each interrupt source is assigned a unique INTEVT code. The start address of the exception
handling routine is the same for all of the interrupt sources. Therefore, the INTEVT value is used
to control branching at the start of the exception handling routine. For instance, the INTEVT
values are suitable for use as branch offsets.
The priority order of the on-chip modules is specified as desired by setting values from 31 to 2 in
INT2PRI0 to INT2PRI7. Values 0 and 1 mask the corresponding interrupt. The priority values for
the on-chip modules are returned to 0 by a reset.
When interrupt sources share the same priority level and are generated simultaneously, they are
handled according to the default priority order given in table 10.12.
Values of INTPRI, INT2PRI0 to INT2PRI7, INTMSK0 to INTMSK2, and INT2MSKR should
only be updated while the BL bit in SR is set to 1, or the corresponding interrupt is masking. To
prevent erroneous interrupt acceptance, clear the BL bit to 0 after having read one of the interrupt
INTC distinguishes between priority levels of H'1A and H'1B,
although both become the same level after rounding off for the CPU.
When multiple interrupt requests from on-chip modules
occur simultaneously, the INTC processes the interrupt with
the higher priority level;
in the case above, the interrupt will be that corresponding to
the H'1B priority level.
However, if an external interrupt request is also generated
at the same time the external interrupt request will have
higher priority if it is;
- an NMI interrupt request
- an IRQ or IRL interrupt request that has the same priority
level or higher priority level (H'D or greater in the case
shown above).
INTC
Priority level: higher (H'1B)
CPU
Priority level:
Interrupt Exception Handling and Priority
1
1
1
1
0
0
Figure 10.3 On-chip Module Interrupt Priority
even (H'D)
1
1
1
1
1
lower (H'1A)
1
1
0
0
1
1
0
Priority level H'01 acts as an interrupt request mask.
INTC
Priority level: H'01
CPU
Priority level: H'0 (interrupt is masked)
Priority level H'01 becomes H'00 with discarding of the
lowest-order bit, so the CPU is not notified of the
corresponding interrupt. The range of priority levels in
the interrupt priority register thus H'02 to H'1F
(30 priority levels).
Rev.1.00 Dec. 13, 2005 Page 301 of 1286
Section 10 Interrupt Controller (INTC)
0
0
0
0
0
0
0
0
1
REJ09B0158-0100