R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 612

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 Direct Memory Access Controller (DMAC)
Notes: 1. Initial value is low level detection.
Rev.1.00 Dec. 13, 2005 Page 560 of 1286
REJ09B0158-0100
Channel Pin Name
3
2. Initial value is low active.
3. This pin is multiplexed with port K7 (GPIO) input/output pin.
4. This pin is multiplexed with MODE2 input pin and port L1 (GPIO) output pin.
5. This pin is multiplexed with MODE0 input pin and port L3 (GPIO) output pin.
6. This pin is multiplexed with port K6 (GPIO) input/output pin.
7. This pin is multiplexed with MODE7 input pin and port L0 (GPIO) output pin.
8. This pin is multiplexed with MODE1 input pin and port L2 (GPIO) output pin.
9. This pin is multiplexed with INTB (PCIC) input pin, AUDATA0 (H-UDI) output pin, and
10. This pin is multiplexed with CE2A (LBSC) output pin, AUDCK (H-UDI) output pin, and
11. This pin is multiplexed with MRESETOUT (RESET) output pin, AUDATA2 (H-UDI)
12. This pin is multiplexed with INTC (PCIC) input pin, AUDATA1 (H-UDI) output pin, and
13. This pin is multiplexed with CE2B (LBSC) output pin, AUDSYNC output pin, and port K0
14. This pin is multiplexed with IRQOUT (INTC) output pin, AUDATA3 (H-UDI) output pin,
DREQ3*
DRAK3*
DACK3*
port K5 (GPIO) input/output pin.
port K1 (GPIO) output pin.
output pin, and port K3 (GPIO) input/output pin.
port K4 (GPIO) input/output pin.
(GPIO) output pin.
and port K2 (GPIO) input/output pin.
2
2
1
*
*
*
13
14
12
Function
DMA transfer request
DREQ3 acceptance
confirmation
DMA transfer end
notification
I/O
Input
Output Notifies acceptance of DMA transfer
Output Strobe output from channel 3 to
Description
DMA transfer request input from
external device to channel 3
request and start of execution from
channel 3 to external device
external device which has output,
regarding DMA transfer request

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