R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 792

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
21.3
Table 21.2 shows the register configuration. Table 21.3 shows the register states in each
processing mode.
Table 21.2 Register Configuration
Notes: 1. To clear the flags, 0s can only be written to bits 7 to 4, 1, and 0.
Rev.1.00 Dec. 13, 2005 Page 740 of 1286
REJ09B0158-0100
Ch.
0
1
Register Name
Serial mode register 0
Bit rate register 0
Serial control register 0
Transmit FIFO data register 0
Serial status register 0
Receive FIFO data register 0
FIFO control register 0
Transmit FIFO data count register 0 SCTFDR0
Receive FIFO data count register 0 SCRFDR0
Serial port register 0
Line status register 0
Serial error register 0
Serial mode register 1
Bit rate register 1
Serial control register 1
Transmit FIFO data register 1
Serial status register 1
Receive FIFO data register 1
FIFO control register 1
Transmit FIFO data count register 1 SCTFDR1
Receive FIFO data count register 1 SCRFDR1
Serial port register 1
Line status register 1
Serial error register 1
2. To clear the flag, 0 can only be written to bit 0.
Register Descriptions
SCBRR0
SCSCR0
SCSPTR0
SCRER0
SCBRR1
SCSCR1
SCSPTR1
SCRER1
Abbrev.
SCSMR0
SCFTDR0
SCFSR0
SCFRDR0
SCFCR0
SCLSR0
SCSMR1
SCFTDR1
SCFSR1
SCFRDR1
SCFCR1
SCLSR1
R/W
R/W
R/W
R/W
W
R/W*
R
R/W
R
R
R/W
R/W*
R
R/W
R/W
R/W
W
R/W*
R
R/W
R
R
R/W
R/W*
R
1
2
1
2
P4 Address
H'FFE0 0000
H'FFE0 0004
H'FFE0 0008
H'FFE0 000C
H'FFE0 0010
H'FFE0 0014
H'FFE0 0018
H'FFE0 001C
H'FFE0 0020
H'FFE0 0024
H'FFE0 0028
H'FFE0 002C
H'FFE1 0000
H'FFE1 0004
H'FFE1 0008
H'FFE1 000C
H'FFE1 0010
H'FFE1 0014
H'FFE1 0018
H'FFE1 001C
H'FFE1 0020
H'FFE1 0024
H'FFE1 0028
H'FFE1 002C
Area 7 Address
H'1FE0 0000
H'1FE0 0004
H'1FE0 0008
H'1FE0 000C
H'1FE0 0010
H'1FE0 0014
H'1FE0 0018
H'1FE0 001C
H'1FE0 0020
H'1FE0 0024
H'1FE0 0028
H'1FE0 002C
H'1FE1 0000
H'1FE1 0004
H'1FE1 0008
H'1FE1 000C
H'1FE1 0010
H'1FE1 0014
H'1FE1 0018
H'1FE1 001C
H'1FE1 0020
H'1FE1 0024
H'1FE1 0028
H'1FE1 002C
Size
16
8
16
8
16
8
16
16
16
16
16
16
16
8
16
8
16
8
16
16
16
16
16
16
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck