R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 498

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
13.2
Table 13.1 shows the pin configuration of the PCIC.
Table 13.1 Input/Output Pins
Rev.1.00 Dec. 13, 2005 Page 446 of 1286
REJ09B0158-0100
Pin Name
AD31 to AD0*
CBE3 to CBE0 C/BE[3:0]
PAR
PCICLK
PCIFRAME
TRDY
IRDY
STOP
LOCK
Input/Output Pins
1
PCI standard
signal name
AD[31:0]
PAR
CLK
FRAME
TRDY
IRDY
STOP
LOCK
I/O
I/O
(TRI)
I/O
(TRI)
I/O
(TRI)
Input
I/O
(STRI)
I/O
(STRI)
I/O
(STRI)
I/O
(STRI)
I/O
(STRI)
Description
PCI Address/Data Bus
Address and data buses are multiplexed. Each bus
transaction consists of an address phase followed by
one or more data phases.
PCI Command/Byte Enable
Bus command and byte enables are multiplexed.
These signals indicate the type of transaction during
the address phase and the byte enables during the
data phases.
PCI Parity
Generates/checks even parity across AD[31:0] and
CBE[3:0].
PCI Clock
Provides timing for all transactions on the PCI bus.
PCI Frame
Current initiator drives this signal, which indicates the
start and duration or end of a transaction.
PCI Target Ready
Selected target drives this signal, which indicates the
target is ready to execute a transaction. During a write,
this signal indicates that the target is ready to accept
data. During a read, this signal indicates that valid data
is present on the AD [31:0] lines.
PCI Initiator Ready
The current bus master drives this signal. During a
write, this signal indicates that valid data is present on
the AD [31:0] lines. During a read, this signal indicates
that the master is ready to accept data.
PCI Stop
Selected target drives this signal to stop the current
transaction.
PCI Lock