R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 310

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
10.3.2
ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection
modes of external interrupt input pins IRQ/IRL7 to IRQ/IRL0. These settings are only valid for
pins configured as individual IRQ interrupts; that is, for pins for which the IRLM0 or IRLM1 bit
in ICR0 is set to 1.
Rev.1.00 Dec. 13, 2005 Page 258 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31, 30
29, 28
27, 26
25, 24
23, 22
21, 20
19, 18
17, 16
15 to 0
R/W:
R/W:
Bit:
Bit:
Interrupt Control Register 1 (ICR1)
Name
IRQ0S
IRQ1S
IRQ2S
IRQ3S
IRQ4S
IRQ5S
IRQ6S
IRQ7S

R/W
31
15

R
0
0
IRQ0S
R/W
30
14

R
0
0
R/W
Initial
Value
00
00
00
00
00
00
00
00
All 0
29
13

R
0
0
IRQ1S
R/W
28
12

R
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
27
11

R
0
0
IRQ2S
R/W
26
10

R
0
0
Description
IRQn Sense Select (n = 0 to 7)
Selects whether the corresponding individual pin
interrupt signal on the IRQ/IRL7 to IRQ/IRL0 pins is
detected on rising or falling edges, or at the high or
low level.
00: The interrupt request is detected on falling edges
01: The interrupt request is detected on rising edges
10: The interrupt request is detected when the IRQn
11: The interrupt request is detected when the IRQn
Note: When either level is selected, the IRQ level
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25

R
0
9
0
IRQ3S
input is at the low level.
input is at the low level.
of the IRQn input.
of the IRQn input.
R/W
interrupt request is not detected unless the
same level is sampled in three consecutive bus-
clock cycles.
24

R
0
8
0
R/W
23

R
0
7
0
IRQ4S
R/W
22

R
0
6
0
R/W
21

R
0
5
0
IRQ5S
R/W
20

R
0
4
0
R/W
19

R
0
3
0
IRQ6S
R/W
18

R
0
2
0
R/W
17

R
0
1
0
IRQ7S
R/W
16

R
0
0
0